This technology not only helps to sustain Moore's Law regarding chip partition and on-chip integration, but also enables off-chip heterogeneous system-level scaling. TSMC-SoIC service platform provides innovative front-end, 3D inter-chip (3D IC) stacking technologies for re-integration of chiplets partitioned from System on Chip (SoC). TSMC SoIC-WoW technology realize heterogeneous and homogeneous 3D silicon integration through wafer stacking process. Mitte des vergangenen Jahres zeigte TSMC ein Package, bei dem zwei 600 mm² große Chips zum Einsatz kamen, an die jeweils vier – also insgesamt … The tight bonding pitch and thin TSV enable minimum parasitic for better performance, lower power and latency as well as smaller form factor. It can incorporate two 600mm² SoCs and 8 HBM2 dies in a 75mm x 75mm package size. A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. “It’s like a single SOC,” TSMC’s Yu said. Like SoC, TSMC-SoIC platform is fully compatible with existing advanced packaging services such as CoWoS® and InFO, offering a powerful "3Dx3D" system-level solution. TSMC is developing “standardized” configurations – e.g., 1 SoC with 2 or 4 HBMs, evolving to >2 SoCs with 8 HBM2Es (96GB @ 2.5TB/sec – wow.) TSMC-SoIC service platform integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip with a smaller footprint and thinner profile, which can be holistically integrated into advanced WLSI (aka CoWoS and InFO ). With the innovative bonding scheme, TSMC-SoIC service platform enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. Meanwhile, TSMC is developing its own hybrid bonding technology. TSMC will use it to develop a 3D-IC technology called System on Integrated Chips (SoIC). Using three reticles, TSMC has demonstrated a technology with a massive 2,460mm² interposer area. Online information and transaction for our customers, The web-based portal for smarter supplier interactions, Copyright © Taiwan Semiconductor Manufacturing Company Limited 2010-, Investor Relations, Public Relations, CSR Contacts. It also affords the flexibility to integrate additional system functionalities. The resulting integrated chip outperforms the original SoC in system performance. SoIC paves the way towards integrating smaller chips with different process nodes in a package. It features ultra-high-density-vertical stacking for high performance, low power, and min RLC (resistance-inductance-capacitance). TSMC-SoIC™ platform is a key technology pillar to advance the field of heterogeneous chiplets integration with reduced size, increased performance. It supports both chip on wafer (CoW) and wafer-on-wafer (WoW) schemes. It also affords the flexibility to integrate additional system functionalities. TSMC-SoIC service platform integrates active and passive chips into a new integrated-SoC system, which is electrically identical to native SoC, to achieve better form factor and performance.