A fabrication process of a semiconductor device, according to the present invention, has an etching step of etching a compound semiconductor wafer employing etching agent consisted of a mixture of at least citric acid solution and hydrogen peroxide solution at a temperature lower than or equal to 15° C. Also, the fabrication process may stop etching by dipping the compound semiconductor wafer into water at a temperature substantially equal to or lower than a temperature of the etching agent, after the etching step. This is because that, in general, the etching speed is abruptly increased according to increasing of a temperature of the etching agent, and in the etching at a temperature lower than or equal to the room temperature, even if the wafer at a temperature lower than the temperature of the etching agent, no critical problem such as overetching may be caused while the etching rate may be lowered slightly at first. In a fabrication process of the semiconductor device, the compound semiconductor may be a field effect transistor which has a gate whose direction is parallel to the [011] direction or the [011] direction on the (100) plane. It should be noted that the mixture ratio of the etching agent is not limited to the shown ratio. 3A and 3B are sections of a semiconductor device fabricated through the preferred embodiment of a fabrication process according to the present invention, in which FIG. For example, an excellent result wherein an etching selection ratio of GaAs versus AlAs is 1450, the standard deviation σVt of the threshold voltage is 13.5 mV , was able to be obtained (M. Tong et al., "A Comparative Study of Wet and Dry Selective Etching Process for GaAs/AlGaAs/InGaAs Pseudomorphic MODFETS", Journal of Electronic Materials, 9-14, Vol. 2 is a graph showing a relationship between a temperature of the etching agent and an etching rate, in which the horizontal axis represents the temperature of the etching agent and the vertical axis represents the etching rate.
In a fabrication process of the semiconductor device, a method for adjusting temperature of the compound semiconductor wafer to be substantially equal to or lower than the temperature of the etching agent, may be to dip the compound semiconductor wafer into water at a temperature substantially equal to or lower than the temperature of the etching agent. By performing etching in this method, influence for surface level due to source resistance, drain lag or so forth can be reduced, and thus the device superior in production yield, reproducibility and uniformity, having no defect, can be fabricated. 5 (1976), and M. Schneider et al., "Characteristics of nonselective GaAs /(Al, Ga)As heterostructure etching at very low etch rate", SPIE Vol. 3B shows a section as (011) plane of the substrate. Furthermore, by setting the gate direction parallel to the [011] direction, etching of the recession is controlled at the (111)B plane. In the preferred embodiment, since etching is performed at a low temperature of 5° C., as shown in FIGS. 1 (1992)). The present invention will be understood more fully from the detailed description given hereinafter and from the accompanying drawings of the preferred embodiment of the present invention, which, however, should not be taken to be limitative to be present invention, but are for explanation and understanding only.

Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. 1A shows a section as the (011) plane of the substrate and FIG. Next, the wafer thus formed is dipped into water at a temperature of 5° C. for about 10 min or longer so that the temperature of the wafer is the same as a temperature of etching agent to be used in the next process step. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention.
It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. IC Fabrication Process Steps y The fabrication of integrated circuits consists basically of the following process steps: y Lithography: The process for pattern definition by applying thin uniform layer of viscous liquid (photo-resist) on the wafer surface. Furthermore, since exposure of the n-AlGaAs layer 4 as the supply layer can be prevented, degradation of characteristics of the device due to gate lag and so forth can be successfully restricted. Also, when the gate is set in the direction parallel to the [011] direction, a device having a gate length of 0.3 μm can be fabricated by setting the thickness of the n-GaAs layer 6 as the contact layer at 200 nm even when a mask opening width is 0.6 μm. Metallization and interconnections. Next, with taking a photoresist as a mask, etching is performed at 5° C. employing a mixture of 50 wt % of citric acid solution and 30 wt % of hydrogen peroxide solution in a volume ratio of 3:1. Thus, enhancement of characteristics, such as rising of frequency of the FET by shortening of channel, and so forth, can be expected. All rights reserved.

generation, System and method for anisotropic etching of silicon nitride, Wet etching station and a wet etching method adapted for utilizing the same, Method and apparatus for fabricating self-assembling microstructures, Method of fabricating semiconductor laser, Method for fabricating self-assembling microstructures, Etchant, etching method, and method of fabricating semiconductor device, Etching solution and etching method for semiconductors and method for evaluating GaAs surface, Etching solution and etching method for semiconductors, Method of fabricating group III-V compound, <- Previous Patent (Method of minimizing...). According to the present invention, even for such large size wafer having large thermal capacity, etching process can be implemented with a relatively small amount of etching agent. In particular, in the (111)B plane, the etching rate is abruptly reduced across about 15° C. Therefore, when the temperature of the etching agent is lower than or equal to 15° C., etching can be performed under the condition where the etching rate is so low as to extremely facilitate control of side etching. Fabrication process of semiconductor device . Semiconductor Device Fabrication: Processes And Equipment, The Argument for New Vs Refurbished Used Photoresist Process Equipment, The Photolithography Process and Its Use In Wafer Level Chip Scale Packing (WLCSP), Lowering Cost of Ownership (COO) “Track” Tools in Back end of the Line (BEOL) Thick Resist Film processes, BEOL Photoresist Processing Tool Considerations, The Spin Coating of Patterned Sapphire Substrates, Taking away material so as to leave behind the desired pattern of materials that create the circuit, Modifying the character of the conductivity of the material, Physical Vapor Deposition (evaporation or sputtering or the like), Epitaxial depostion (meaning along the same axis so following the structure of the material, this is a special case of CVD), Wafer cleaning (this is to remove unwanted contaminants), Dry etch typically using plasma technology, Photoresist develop (which itself is a sort of etch), Injecting ions into the crystal structure by ion implantation, usually followed by an anneal step to “heal” the damage done by the implantation. 1B shows a section as the (011) plane of the substrate. In a method employing a dry etching method in order to avoid the side etching, problems are encountered as requiring a large scale device and as being possible to cause damage to the semiconductor device for performing physical polishing. A compound semiconductor wafer is dipped into water at a temperature of 5° C. for about 10 seconds to preliminarily adjust to a temperature substantially equal to a temperature of etching agent. The photo-resist is hardened by baking and than selectively removed by projection of light through a reticle containing mask information. For instance, the present invention should be applicable for an InGaAs/AlGaAs type semiconductor device, an InGaAs/InAlAs type semiconductor device, an InGaAs/InP type semiconductor device, an InAlAs/InP type semiconductor device and the like. It should be noted that while the sufficient effect was obtained by dipping the wafer into water at a temperature of 5° C. for about 10 seconds in the shown embodiment, the period for dipping the wafer is variable depending upon thermal conductivity of the wafer and thus not specifically limited.

In contrast to this, in the conventional method, etching for a 3 inch wafer would require greater than or equal to 500 cc of the etching agent. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodied within a scope encompassed and equivalents thereof with respect to the features set out in the appended claims. The citric acid type etching agent has high etching selection ratio of GaAs versus Alx Ga1-x As (0≤x≤1) and thus permits fabrication of a device superior in uniformity of a threshold voltage. United States Patent 6093657 . FIGS. Therefore, the present invention achieves saving of the etching agent to be one tenth of the conventional method. Therefore, formation of side etching in the device can be avoided. Fabrication process of a semiconductor device having an interconnection structure Download PDF Info Publication number US5976971A. FIGS. It can be integrated with a coater and/or developer subsystem. Steppers focus, align and move the image of the mask or reticle.